In conventional data communication networks, there is an issue of the data packet drop rate as a result of the physical interface error rate, i.e., data packets are dropped as a result of errors introduced into the packets due to the physical interface. If, for example, there is a physical error rate of 10e-12, then for an interface of 1 Tb/sec, one packet will be dropped every 1 second. This issue becomes serious as typical interfaces, that currently transfer data at speeds in the range of 10 Gb/sec, become much faster and reach the range of 1 Tb/sec (1012 b/sec). At these speeds, physical error rates that were in the range of 10−18 can drop to 10−12. In other words, while the packet drop rate for a 10 Gb/sec line with an error rate of 10−18 can be as low as one packet drop every 3 years, the rate can rise to a packet drop every 1 second for an interface of 1 Tb/sec with a physical error rate of 10−12. With new requirements for very high bit rate transmission between chips in modern equipment, this packet drop number is unacceptable.
There are known a number of interconnect protocols for use at high transmission speeds. These protocols transmit over a number of channels in parallel. Since conventional ECC (Error Correcting Code) provides protection only for serial data transmission, different protection is required for parallel channels.
One example of a high speed chip-to-chip interconnect protocol is called Interlaken. Interlaken is a scalable chip-to-chip interconnect protocol designed to enable transmission speeds from 10 Gbps to 100 Gbps and beyond. Using the latest SERDES (serialize-de-serialize) technology and a flexible protocol layer, Interlaken minimizes the number of connection pins and power overhead of chip-to-chip interconnects and provides a scalable solution that can be used throughout an entire system. In addition, Interlaken uses error checking and a data scrambler to ensure data integrity and link robustness.
There are two fundamental structures that define the Interlaken Protocol: the data transmission format and the Meta Frame. Data sent across the interface is segmented into bursts, which are subsets of the original packet data. Each burst is bounded by two control words, one before and one after, and sub-fields within these control words affect either the data following or preceding them, for functions like start-of-packet, end-of-packet, error detection, etc. The Meta Frame is defined to support the transmission of the data over a SERDES infrastructure. It encompasses a set of four unique control words, which are defined to provide lane alignment, scrambler initialization, clock compensation, and diagnostic functions. The Meta Frame runs in-band with the data transmissions, using the specific formatting of the control words to distinguish it from the data.
Currently, the basic word that is transferred by the Interlaken protocol is 67 bits wide, where 64 bits are data and 3 bits are framing bits. Incorporated in these 67 bits are error detection bits, e.g., CRC (Cyclical Redundancy Checking). However, while this CRC protection for the data bits will guarantee (to some extent) that error packets will be detected and dropped, it will not improve the drop rate.
As stated above, the Interlaken protocol defines control words and data words. Each control word has 24 bits of CRC in it that protect the control word itself and all the data words in the frame until the next control word. The minimum number of data words between two control words is 4 and the maximum number of data words between two control words is not limited by the protocol. A typical number of data words between control words is 32. However, this protection is limited to certain transmission rates.
Accordingly, it would be very desirable to provide protection for parallel transmissions over a plurality of channels, so as to minimize the packet drop rate during high speed data transfer, particularly for use with the Interlaken protocol.
Chip-to-Chip interfaces are used for communicating data between two neighbor chips in the same box. The interface can be implemented using SerDes technology, to meet high bandwidth requirements for transferring high-rate data between chips.
SerDes technology is very efficient for transferring data between two chips. SerDes units can operate at a very high speed and can serialize data, which results in fewer pins in the chip package.
However, the error rate in chip-to-chip communications can be high and can result in lost data. Therefore, there is a need for error correcting codes that minimize or eliminate the error rate.